This invention relates to a static induction transistor logic device (hereafter called SITL), and particularly to a method of forming the gate region thereof by ion implementation and bringing the maximum of the diffusion potential induced in the channel thereof closer to the source of the device.
The conventional SITL comprises an injector 5 and the static induction transistor for switching a conductive path between the substrate 1 acting as the source thereof and the drain 4 by controlling a height of a barrier with changing a potential of the gate region 3 which is used for the barrier of carrier transfer. The barrier is caused by a diffusion potential which is made from a junction between the epitaxial layer 2, having a sufficient low impurity concentration and formed on the substrate by the epitaxial method or the like, and the gate region 3 having a high impurity concentration and a polarity opposite that of the epitaxial layer 2 as shown in FIG. 1.
For example the substrate 1 is N.sup.+, the epitaxial layer 2 is formed N.sup.-, the gate region 3 and the injector 5 are P.sup.+ and the drain 4 is N.sup.+. Hitherto the said P.sup.+ gate region 3 has been formed by heat-diffusion of boron (B) and the shape of gate region 3 (P.sup.+ region) becomes arc shaped in section having radius r centering around the mask ends A before diffusion according to the diffusion time of the boron as shown in FIG. 2. As a result, the distribution of a diffusion potential caused by the junction between the P.sup.+ of gate region 3 and the N.sup.- of epitaxial layer 2 has a distribution as shown on the dotted line in the FIG. 2. The potential becomes higher toward the arrow directions and the maximum value of the potential P occurs at a distance X from the substrate 1 come out a source as shown by the curve a of FIG. 3 from the view of B-B' portion of intrinsic channel region. In the case that the maximum potential is located at a distant X from the source, when the gate has a positive bias (curve b) applied thereto and the drain also has a positive bias (curve c) applied thereto, it takes time for electrons injected from the source to reach the point of maximum potential P by diffusion transfer. Therefore, conventional SITL is not suitable for high frequency operation. An attempt to bring the point of maximum potential P closer to the source has been to form the lower parts of gate-region 3 during the growth of epitaxial layer 2, and with the rest of the gate region 3 diffused into the epitaxial layer after the epitaxial layer has been grown.
In this construction, the point of maximum potential P is located at the narrowest portion of the space inside the gate, so that in spite of improving the characteristic, the fabricating process is made more complex which results in lowering the yield rate and increasing the cost of fabrication.